What are the advantages and limitations to multi-stage sampling?
Answer:
On the plus side you get to sample all the chocolates and candies coming down the line.
The bummer is, you'll get a tummy ache and gain weight.
I'm assuming you're referring to the sampling of an asynchronous input to a synchronous digital circuit. Sampling is usually performed by 1 or more stages of D-type flip flops in a shift register configuration. The "metastability" of these flops is critical to the performance of the circuit. Metastability occurs when the transition of an input to a flip flop violates its setup and hold specs. If this occurs, the output of the flop can oscillate for a period of time before it settles to a logic 1 or 0. IC manufacturers should specify a probability distribution for this settling time. For a 2 stage sampler, for example, if there's a 90% chance that the flop's oscillations will settle in 1 microsecond, and the setup time to the 2nd flop is 1 uS, than running the sampler at 1/(1 + 1) uS = 500 KHz will assure a stable output 90% of the time (which, by the way, is not very good). The more stages you provide, the lower the probability that the output of the sampler will become metastable at a given clock frequency. Needless to say, you want the probability that the output of a sampling circuit will go metastable to be as close to zero as possible. A typical input to a synchronous circuit may toggle a billion times in the course of a day, and every one of these transitions must be accurately detected if your circuit is to work.
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